正版新书]EDA技术与Verilog HDL(英文版)黄继业9787302539278

Chapter 1 Introduction
1.1 EDA Technology
1.2 Object for EDA Technology
1.3 Common Hardware Description Languages
1.4 Advantages of EDA Technology
1.5 Development Flow for FPGA and CPLD
1.5.1 Design Input
1.5.2 Synthesis
1.5.3 Fit (Place and Route)
1.5.4 Simulation
1.5.5 RTL Description
1.6 Programmable Logic Devices
1.6.1 Classification of PLD
1.6.2 Programming Principle of PROM
1.6.3 GAL
1.7 Structure and Programming Principle of CPLD
1.8 Structure and Working Principle of FPGA
1.8.1 Logical Structure of LUT
1.8.2 Structural Principle of Cyclone 4E Series Devices
1.8.3 FPGA Device with Embedded Flash
1.8.4 Major Manufacturers of FPGA
1.9 Hardware Testing Technology
1.9.1 Internal Logic Test
1.9.2 JTAG Boundary Scan Test
1.10 Programming and Configuration
1.11 Quartus
1.12 IP Core
1.13 Major EDA Software Companies
1.14 Development Trend of EDA
Exercises
Chapter 2 Program Structure and Data Type
2.1 Verilog Program Structure
2.1.1 Expression of Verilog Module
2.1.2 Signal Name and Mode of Verilog Module Port
2.1.3 Definition of Verilog Signal Type
2.1.4 Function Description of Verilog Module
2.2 Data Types of Verilog
2.2.1 Net Type
2.2.2 Definition of Wire Type Variable
2.2.3 Register Type
2.2.4 Definition of Register Type Variable
2.2.5 Definition of Integer Type Variable
2.2.6 Memory Type
2.3 Verilog Syntax Rules
2.3.1 Four Logical States in Verilog
2.3.2 Digital Expression Forms of Verilog
2.3.3 Expression of Data Type
2.3.4 Constant
2.3.5 Identifiers, Keywords, and Other Syntax Rules
2.3.6 Usage of parameter and localparam
Exercises
Chapter 3 Behavioral Statements
3.1 Procedural Statement
3.1.1 always Statement
3.1.2 The Application of always Statement in D flip-flop Design
3.1.3 The Application of Multi-Process and Asynchronous Sequential Circuit Design
3.1.4 Verilog Expression of Simple Up Counter
3.1.5 initial Statement
3.2 Block Statement
3.3 case Conditional Statement
3.4 if Conditional Statement
3.4.1 General Expression of if Statement
3.4.2 Combinational Circuit Design Based on if Statement
3.4.3 Sequential Circuit Design Based on if Statement
3.4.4 Design of DFF with Asynchronous Reset and Clock Enable
3.4.5 Design of DFF with Synchronous Reset
3.4.6 Design of Latches with Clear
3.4.7 Characteristics and Rules of Clock Procedural Statement
3.4.8 Practical Up Counter Design
3.4.9 Shift Register Design with Synchronized Preset Function
3.4.10 Conditional Instructions in if Statements
3.5 Statement of Procedural Assignment
3.6 Loop Statement
3.6.1 for Statement
3.6.2 while Statement
3.6.3 repeat Statement
3.6.4 forever Statement
3.7 task and function Statements
Exercises
Chapter 4 FPGA Hardware Implementation
4.1 Code Editing Input and System Compilation
4.1.1 Design File Edit and Input
4.1.2 Creating a Project
4.1.3 Constraint Item Setting
4.1.4 Comprehensive Synthesis and Compilation
4.1.5 Application of RTL Viewer
4.2 Timing Simulation
4.3 Hardware Testing
4.3.1 Pin Assignment
4.3.2 Compiled File Download
4.3.3 Indirect Programming of Configuration Chip through JTAG
4.3.4 USB-Blaster Driver Installation
4.4 Circuit Schematic Design Flow
4.4.1 Half-adder Design
4.4.2 Top-level Design of Full-adder
4.4.3 Timing Simulation and Hardware Testing of Full Adders
4.5 Pin Assignment Using Attributes
4.6 Usage of SignalTap II
4.7 Trigger Signal Edit of SignalTap II
4.8 Installation of Quartus II 13.
Exercises
Labs and Designs
Lab 4-1 Multiplexer Design
Lab 4-2 Hexadecimal 7-segment Digital Display Decoder